As an aid to understanding the problems in prior art methods and apparatus, reference should be made to FIGS. 1A-1F which illustrate a typical series of steps used in electron beam, photo aided, or lithographic processes to manufacture semiconductor devices. Referring to FIG. 1A, a semiconductor substrate 1, such as a slice or wafer of silicon or other composite has grown thereon an insulating oxide layer 2, such as silicon dioxide. A series of steps is undertaken to cut a window or pattern in the silicon dioxide layer and expose a predetermined area of the underlying substrate 1. Referring to FIG. 1B and using like reference numerals for like items, a film of photoresist 3 is coated onto the entire surface of the oxide layer 2. Like photographic film, the photoresist is sensitive to incident radiation, such as an electron beam, visible light, ultraviolet light, or X-rays.
Referring to FIG. 1C, a traveling electron beam 4 is moved across the photoresist to expose selected portions. The beam is directed in a manner to expose the photoresist according to a pattern traced or "written" by the beam. This is referred to as maskless or direct processing, and it delineates an exposure pattern by writing directly on the photoresist. Since the electron beam has a shorter wavelength and greater depth of field than many other types of radiation, it is capable of forming very fine exposure patterns, and it eliminates the need to create a cumbersome physical mask, as used with ultraviolet processing, which is time consuming and very costly. In FIG. 1C the exposed portion is indicated by the stippled area 3a. That portion of the photoresist labeled 3b is not exposed to the incident radiation and is not affected thereby.
Referring to FIG. 1D, the photoresist is subjected to a process that dissolves and removes the exposed photoresist 3a but does not affect the unexposed photoresist. This leaves a pair of spaced parallel strips 3b of unexposed photoresist separated by a channel 2a of the underlying oxide layer 2. Referring to FIG. 1E, the unexposed photoresist 3b and the oxide layer 2a are treated so as to remove the unprotected oxide, but not the unexposed photoresist 3b, in order to expose a channel 1a of the underlying material 1. Referring to FIG. 1F, the unexposed photoresist 3b has been stripped from the oxide layer in preparation for succeeding process steps, leaving a channel of bare silicon defined by strips of superposed silicon dioxide 2.
The desire to increase circuit density on semiconductor material and recent developments in photo aided processes have resulted in the ability to create smaller and smaller circuit elements. Typically, these elements are on the order of a few microns in size or smaller, and they may be composed of layers on the order of only 0.01 microns deep. Thus, it is increasingly important that succeeding processing steps do not disturb the effects of earlier steps, and, for this reason, it is desirable to control the energy of the electron beam or other radiation used to expose the photoresist.
In the past the energy of the incident electron beam was not controlled to match the amount of energy required to expose the photoresist or the thickness or depth of the photoresist at a given location. Instead, the electron beam voltage and charge was fixed at a level high enough to expose the thickest portions of the photoresist layer without regard to any problems that might arise where the photoresist was thinner, or where there were other variations in the photoresist coating, or where the underlying structures were "tall," or where the underlying layers were susceptible to damage from the incident electron beam radiation. Some attempts have been made to ameliorate scattering of the electron beam by varying total incident dosages, but this was done at a constant accelerating voltage and without regard to variations in the photoresist thickness. As a result, the electron beam had excess energy in some sectors and the electrons penetrated to the underlying layers or substrate, resulting in unwanted damage. For example, unwanted damage was inflicted upon insulated gate field effect transistors (IGFET) when the accelerating voltage of the electron beam used to expose the photoresist was too high and the electrons penetrated through the photoresist and overlying films to the gate insulator. Experiments have demonstrated that it is desirable to limit the energy density in the underlying layers to less than 10.sup.5 or 10.sup.6 Rads SiO.sub.2.
To achieve exposure of the photoresist in a typical electron beam system, the electrons are accelerated to 20 to 25 kilovolts (KeV), or even as high as 50 KeV, and the photoresist is subjected to dosages of 20 to 30 microcoulombs per square centimeter. At such levels of dosage and at these accelerating voltages, the incident electrons pass through typical thicknesses of photoresist, i.e. two to three microns, and damage the underlying films and semiconductor materials. This produces fixed positive charge and neutral traps, which are undesirable. Prior to the application of a metalizing layer, it was believed that such damage could be annealed by heating the semiconductor wafers in a hydrogen-containing ambient atmosphere in the 550.degree.-700.degree. C. range. However, it has recently been claimed that following repetitive, high energy radiation damage to the gate insulator of a MOS capacitor, even vigorous annealing treatments do not correct the damage done. See A. Reisman et al., "The Effects of Pressure, Temperature and Time on the Annealing of Ionizing Radiation Induced Insulator Damage in N-channel IGFET's," Journal of the Electrochemical Society, Vol. 130 No. 6, June 1983; and A. Reisman et al, "On the Removal of Insulator Process Induced Radiation Damage from Insulated Gate Field Effect Transistors at Elevated Pressure," Journal of the Electrochemical Society, Vol. 128, No. 7, July 1981. Moreover, excessive exposure to high temperatures may alter doping levels or configurations, or unduly stress the lattice structure. Accordingly, there is a great need to minimize the damage caused by the use of high energy electrons and other ionizing radiation during the manufacture and processing of semiconductors.
The present invention is based upon the recognition that proper exposure of the photoresist is a function of the energy absorbed by it rather than the accelerating voltage of the electron beam or the amount of charge carried by the beam alone. Stated otherwise, the extent of radiation damage is a function of the total energy absorbed in a given mass of material and not the energy per photon or energy per electron. Thus, the present invention involves matching the energy of the incident electron beam and electron dose to the amount of energy locally required to thoroughly expose the photoresist. This is done by controlling the voltage and the amount of charge of the incident electron beam to correlate to variations in the photoresist thickness. By controlling the voltage, the electron beam will penetrate a predetermined distance with minimal penetration to underlying structures, and by controlling the amount of charge carried by the electron beam, the energy of the electron beam is controlled to thoroughly expose the photoresist.
The present invention also has applications in compensating for proximity effects encountered in electron beam processes, and for accommodating topographical variations resulting from the layered construction of the semiconductor.
Thus, it is an object of the present invention to provide a method and apparatus for exposing photoresist with an electron beam during the fabrication of semiconductor devices by controlling the voltage and the amount of charge of the electron beam to minimize ionizing radiation damage to the underlying films and semiconductor substrate.
It is a further object of the present invention to provide a method and apparatus for exposing photoresist with an electron beam during the fabrication of semiconductor devices by controlling the voltage of the electron beam to substantially penetrate the entire depth of the photoresist thickness with minimal penetration therethrough to the underlying structures.
It is a still further object of the present invention to provide a method and apparatus for exposing photoresist with an electron beam during the fabrication of semiconductor devices by controlling the voltage and the amount of charge of the projected electron beam as it is deflected to match the total energy of the electron beam to the amount of energy absorbed by the photoresist during exposure from an incident electron beam.
Accordingly, the present invention is a method and apparatus for exposing photoresist with an electron beam during the fabrication of a semiconductor device. The method includes coating a substrate with a photoresist. An electron beam is projected onto the photoresist and deflected to expose the photoresist in a predetermined pattern. The voltage and the amount of charge of the electron beam are controlled as the beam is deflected so that the energy incident upon the photoresist from the electron beam is correlated to variations in the photoresist thickness to expose the photoresist with no significant penetration therethrough to the underlying structures.